1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a DRAM (Dynamic Random Access Memory) in which a short-circuit margin between a fine contact hole formed by self alignment and an adjacent wiring line has been increased.
2. Description of the Related Art
It is a mainstream trend recently that a DRAM is imparted with a COB (Capacitor Over Bit-line) structure because of the feasibility in ensuring the capacity of the capacitors. In the COB structure, main components of the memory cells include word lines formed on a surface of a semiconductor substrate, bit lines arranged over the word lines through an interlayer insulating film so as to be perpendicular to the word lines, and capacitors formed above the bit lines through an interlayer insulating film. Each of the capacitors arranged uppermost is connected to the semiconductor substrate through contact plugs formed threading through gaps between the word lines and the bit lines, so as not to cause short circuiting with the lines.
An example of a structure of memory cells in a DRAM will further be described in detail with reference to a plan view of FIG. 1 and a cross-sectional view of FIG. 2.
As illustrated in the plan view of FIG. 1, active regions 101a each surrounded by element isolation regions 102 are regularly arranged to stand in rows. Word lines 105 are arranged to traverse plurality of active regions 101a, with each of word lines 105 being provided with a sidewall 105d at both sides thereof. The word lines constitute the gate electrodes of the transistors formed on active regions 101a. Bit lines 111 are arranged being substantially perpendicular to the word lines. Further, drains 103 and sources 104 are provided as diffusion layers for the transistors formed in the active regions. Contact plugs 107a and 108a are provided on each drain 103 and source 104, respectively, so as to be connected to upper wiring. Each contact plug 107a is connected to bit line 111 and each contact plug 108a is connected to a capacitor provided on an upper layer portion.
The cross-sectional view of FIG. 2 schematically illustrates a cross section taken along a line A-A of FIG. 1. Element isolation regions 102 as well as drains 103 and sources 104, each made up of an n-type diffusion layer, are provided in predetermined regions in a surface of p-type semiconductor substrate 101. The word lines each consisting of gate electrode 105b and protection insulating film 105c are provided through gate insulating film 105a formed on the surface of semiconductor substrate 101. Each of the word lines is provided with sidewalls 105d. First interlayer insulating film 106 is provided to cover the word lines. Contact holes 107 and 108 are provided in predetermined regions of first interlayer insulating film 106, while contact holes 107 and 108 are provided with contact plugs 107a and 108a, respectively. Second interlayer insulating film 109 is provided on the surfaces of contact plugs 107a and 108a and first interlayer insulating film 106. Bit line contact plugs 110 are provided so as to be connected to respective contact plugs 107a. Also, second contact plugs 110a each serving as a part of a capacitor contact plug are provided so as to be connected to respective contact plugs 108a. Bit lines 111 are provided on respective bit line contact plugs 110, while bit lines 111 are covered with third interlayer insulating film 112. Third interlayer insulating film 112 is provided with capacitor contact plugs 113 each of which is positioned between bit lines 111 and connected to second contact plug 110a. Fourth interlayer insulating film 114 is provided on the surfaces of capacitor contact plugs 113 and the third interlayer insulating film, while cylinder holes are formed in the fourth interlayer insulating film so as to be located at positions corresponding to respective capacitor contact plugs 113. Lower electrode 115 is provided at an inner surface of each cylinder hole so as to be connected to capacitor contact plug 113. Capacitor insulating film 116 and upper electrodes 117 are provided to cover lower electrodes 115. Further, wiring layer 119 is provided through fifth interlayer insulating film 118, whereby memory cells having the COB structure are constituted.
The memory cells in a DRAM having the COB structure as described above have been downsizing with the demand for enhancing its integration density. This also necessitates the reduction of a planar area allowed for each component, and thus formation of the contact plugs mentioned above has also become considerably difficult. In particular, formation of contact plugs 107a and 108a between adjacent word lines and formation of each capacitor contact plug 113 between bit lines 111 have been brought into a more difficult situation because of the reduced processing margins. In order to reduce such difficulties, SAC (Self Aligned Contact) processes have been used for forming contact holes.
However, even the use of the SAC processes has allowed the following problem to come up to the surface. Referring to cross-sectional views illustrated in FIGS. 3A and 3B, the problem is explained.
As shown in FIG. 3A, word lines, each consisting of gate electrode 105b and protection insulating film 105c made up of a silicon nitride film, are formed first, and sidewalls 105d, each made up of a silicon nitride film, are also formed. After that, first interlayer insulating film 106 made up of a silicon oxide film is formed overall, followed by forming hard mask layer 130. Then, using photolithography, photoresist pattern 131 is formed to transfer the hole pattern to hard mask layer 130 so that hard mask 130a is formed.
Subsequently, as shown in FIG. 3B, dry etching is carried out to etch first interlayer insulating film 106 made up of a silicon oxide film by using photoresist pattern 131 and hard mask 130a as a mask. In this case, since etching selection ratio cannot be sufficiently ensured between the silicon oxide film and the silicon nitride film, etching of the silicon oxide film down to the surface of the semiconductor substrate involves etching of the silicon nitride film at shoulder portions of each gate electrode 105b. As a result, the thickness of a portion in the insulating film indicated by a circle B is reduced, raising a problem of short circuiting between a contact plug, which will be formed subsequently, and the gate electrode. In dry etching, since a smaller diameter of a hole permits the speed of etching of the hole bottom to become relatively slower, this problem will become more serious as the memory cells are more miniaturized.
To avoid the problem explained above, Japanese Patent Laid-Open No. 2003-197775 (D1) suggests performing an SAC process using an organic film having low dielectric constant. According to a method disclosed in D1, gate electrodes each having a spacer at sidewalls thereof are formed first, followed by forming an organic film having low dielectric constant overall, the height of the organic film being substantially the same as that of each gate electrode, so that spaces between the gate electrodes are buried by the film. Then, an inorganic insulating film is stacked overall, followed by forming predetermined holes in the inorganic insulating film using lithography and dry etching. Then, using the inorganic insulating film as a mask, the organic film having low dielectric constant is dry etched using an etching gas whose main content is oxygen to thereby form contact holes.
D1 discloses various organic films having low dielectric constant. Material of each of the films is a carbon film formed by a CVD (Chemical Vapor Deposition) process or an organic coating film containing silicon or fluorine. The former, i.e., the carbon film formed by the CVD process, has a poor step-covering property and thus voids are formed in the film, which resultantly raises a problem of short circuiting between the contact holes through the voids. The latter, i.e., the organic coating film, has a poor heat resistance and thus may raise a problem of heat deformation of a pattern or degassing in manufacturing steps that require use of heat of 500° C. or more. D1 describes a side benefit of reducing parasite capacitance in the wiring by taking an approach of leaving the organic film having low dielectric constant as it is. In this case, however, heat load imposed during a step following the formation of the organic film having low dielectric constant, is required to be limited to 500° C. or less. Thus, application of this approach to a semiconductor device, such as a DRAM, is problematically difficult because of a later step of imposing heat load of about 700° C. In addition, although not specifically described in D1, if contact plugs are formed of tungsten in each of these organic coating films, there may be a problem that the organic coating film is etched by fluorine contained in a raw material of tungsten.